The present invention generally relates to logic circuits, and more particularly to a multiple-input logic circuit having a complementary metal oxide semiconductor (CMOS) structure for carrying out an exclusive-OR (even parity check) or an exclusive-NOR (odd parity check) operation.
As will be described later on in conjunction with the drawings, a conventional 2-input exclusive-OR logic circuit having a CMOS structure comprises sixteen transistors. A signal passes through a maximum of three gates between an input and an output of such a 2-input exclusive-OR logic circuit. In the case of a conventional 3-input exclusive-OR logic (even parity check) circuit having the CMOS structure, thirty-eight transistors are required.
Accordingly, the conventional exclusive-OR logic circuits suffer problems in that a large number of elements are required, a signal must pass through a large number of gates between the input and the output of the exclusive-OR logic circuit, and the operation speed of the logic circuit is slow for this reason. In addition, when an inverted signal of an output signal of the exclusive-OR logic circuit is to be obtained, it is necessary to add an inverter, and there are problems in that the number of elements increases and the operation speed becomes even slower because of the increased number of gates.